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HANBit
HMD4M32M8GL
16Mbyte(4Mx32) Fast Page Mode, 4K Refresh 72Pin SIMM Part No. HMD4M32M8GL GENERAL DESCRIPTION
The HMD4M32M8GL is a 4M x 32bit dynamic RAM high-density memory module. The module consists of eight CMOS 4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
FEATURES
w Part Identification HMD4M32M8GL- 4,096 Cycles/64ms Ref . Gold w Access times : 50, 60ns w High-density 16MByte design w Single + 5V 0.5V power supply w JEDEC standard pinout w FP(Fast Page) mode operation w TTL compatible inputs and outputs w FR4-PCB design 1 2 3 4 5 6 Vss DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 Vcc /WE0 A0 A1 A2 A3 A4 A5 A6 A7 DQ4 DQ20 DQ5 DQ21 DQ6 PIN SYMBOL
PIN ASSIGNMENT
PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SYMBOL DQ22 DQ7 DQ23 A8 A10 Vcc /WE2 NC Vss /RAS Vcc NC NC /OE0 Vss /CAS Vcc NC NC NC A9 A11 /WE1 Vcc PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SYMBOL DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 /WE3 DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 Vss NC NC BDIN NC SIZE Vss
OPTIONS
w Timing 50ns access 60ns access w Packages 72-pin SIMM
MARKING
-5 -6 M
7 8 9 10 11 12 13
PIN CONFIGURATION DESCRIPTION
Pin Name A0 - A11 A0 - A10 DQ0-31 /WE0-/WE3 /OE /CAS /RAS BDIN SIZE Vcc/ Vss NC
URL: www.hbe.co.kr REV.1.0. (August. 2002)
FUNCTION Address Input(4K Ref.) Address Input(2K Ref.) Data In/Out Read/Write Input Data Output Enable Column Address Strobe Row Address Strobe Board Insertion Signal Size Indentification Power and Ground No Connection 14 15 16 17 18 19 20 21 22 23 24
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FUNCTIONAL BLOCK DIAGRAM
CAS RAS W OE
HMD4M32M8GL
/CAS /RAS /WE0
U1
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ0-DQ3
CAS RAS W OE
U2
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ4-DQ7
/WE1
CAS RAS W OE
U3
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ8-DQ11
CAS RAS W OE
U4
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ12-DQ15
CAS RAS W OE /WE2
U5
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ16-DQ19
CAS RAS OE W
U6
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ20-DQ23
CAS RAS W OE /WE3
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
U7
DQ24-DQ27
CAS RAS W OE /OE A0-A10(A11)
U8
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ28-DQ31
Vcc Vss
0.1uF or Capacitor for each DRAM 0.22uF To all DRAMs
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG
HMD4M32M8GL
RATING -1V to 7.0V -1V to 7.0V 8W -55oC to 150oC
Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 4.5 0 2.4 -1.0 TYP 5.0 0 MAX 5.5 0 Vcc+1 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS
SYMBOL ICC1 SPEED -5 -6 ICC2 -5 ICC3 -6 -5 ICC4 ICC5 ICC6 -5 -6 Il(L) IO(L) VOH VOL ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min ) ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min )
URL: www.hbe.co.kr REV.1.0. (August. 2002)
MIN -40 -40 2.4 -
MAX 720 640 16 720 640 640 560 8 720 640 40 40 0.4
UNITS mA mA mA mA mA mA mA mA mA mA A A V V
-6
ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.)
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ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V VIN 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V VOUT 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA )
HMD4M32M8GL
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
o
CAPACITANCE
( TA=25 C, Vcc = 5V, f = 1Mz ) SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1
o
DESCRIPTION Input Capacitance (A0-A11) Input Capacitance (/WE0-/WE3) Input Capacitance (/RAS) Input Capacitance (/CAS) Input/Output Capacitance (DQ0-31)
MIN -
MAX 40 49 49 49 49
UNITS pF pF pF pF pF
AC CHARACTERISTICS
( 0 C TA 70oC , Vcc = 5V10%, See notes 1,2.) -5 -6 UNIT MIN MAX MIN 110 50 13 25 0 0 3 30 50 13 50 13 20 15 5 0 10 0 10K 37 25 10K 13 50 0 0 3 40 60 15 60 15 20 15 5 0 10 0 10K 45 30 10K 15 50 60 15 30 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 90
STANDARD OPERATION Random read or write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time /RAS to column address delay time /CAS to /RAS precharge time Row address set-up time Row address hold time Column address set-up time
URL: www.hbe.co.kr REV.1.0. (August. 2002)
SYMBOL tRC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC
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Column address hold time Column address hold referenced to /RAS Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command hold referenced to /RAS Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Data-in hold referenced to /RAS Refresh period 2K Ref. Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge to /CAS hold time Access time from /CAS precharge Fast page mode cycle time /CAS precharge time (Fast page) /RAS pulse width (Fast page ) /W to /RAS precharge time (C-B-R refresh) /W to /RAS hold time (C-B-R refresh) /CAS precharge(C-B-R counter test) NOTES tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tREF tWCS tCSR tCHR tRPC tCPA tPC tCP tRASP tWRP tWRH tCPT 35 10 50 10 10 20 200K 0 5 10 5 30 10 40 25 0 0 0 10 40 10 15 13 0 10 40 32
HMD4M32M8GL
10 45 30 0 0 0 10 45 10 15 15 0 15 45 32 0 5 10 5 35 40 10 60 10 10 20 200K ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.An initial pause of 200s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 2TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that tRCD tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS tWCS(min) the cycle is an early write
URL: www.hbe.co.kr REV.1.0. (August. 2002) HANBit Electronics Co.,Ltd.
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cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle.
HMD4M32M8GL
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
TIMING DIAGRAM
Please refer to attached timing diagram chart (I)
URL: www.hbe.co.kr REV.1.0. (August. 2002)
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HMD4M32M8GL
URL: www.hbe.co.kr REV.1.0. (August. 2002)
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HMD4M32M8GL
URL: www.hbe.co.kr REV.1.0. (August. 2002)
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PACKAGING INFORMATION
SIMM Design
HMD4M32M8GL
3.38 0.2mm
25.4 0.2mm
6.35 0.2mm
6.35 0.2mm
6.35 0.2mm
95.25 0.2mm
2.54 mm MIN 0.25 mm MAX
1.27
Gold : 1.040.10 mm Solder:0.9140.10mm
1.270.08m
ORDERING INFORMATION
Part Number Density Org. Package Refresh Cycle 4K Cycles 64ms Ref. 4K Cycles 64ms Ref. Vcc SPEED
HMD4M32M8GL-5 HMD4M32M8GL-6
16MByte 16MByte
4MX 32bit 4MX 32bit
72 Pin-SIMM 72 Pin-SIMM
5.0V 5.0V
50ns 60ns
URL: www.hbe.co.kr REV.1.0. (August. 2002)
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